Select the Correct Debug Methodology for Your Altera FPGA Design

Debug can on average take up to 50% of the development time, particularly when looking for a difficult issue. We therefore need to use innovative ways to speed up the flow. Tektronix, First Silicon Solutions (FS2), and Alterahave teamed up to provide a robust solution to enable quick identification and troubleshooting of even the most difficult bugs. This application note discusses how to select the correct debug methodology for your Altera FPGA design.

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54W-21382-0 (WebID: 12493), 24-Jan-2008

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