Reference Clock Jitter and Data Jitter

Reference clock jitter sets the ultimate limit on the bit error ratio of a serial data system.
The traditional techniques for quantifying jitter on clock signals don't help system
designers estimate the clock's contribution to the total jitter defined at a bit error ratio.
New techniques are being introduced to model how transmitters and receivers use
reference clocks so that the system RJ and DJ attributable to the reference clock can be
measured and maximums specified. This installment of Jitter 360 shows how reference
clock jitter affects data jitter at each point in the system and describes techniques for its
analysis.

Download File (458 KB) 8 Pages

55W_21992_0 (WebID: 12844), 08-Apr-2008

Navigate Application Notes and Technical Documents

Application Notes and Technical Documents > Applications > Serial Data > Jitter, Noise & Link Analysis

Application Notes and Technical Documents > Products > Oscilloscopes > Oscilloscopes 5GHz and above > Discontinued Oscilloscopes > CSA7000B Series (discontinued)

Application Notes and Technical Documents > Products > Oscilloscopes > Oscilloscopes 500MHz to 5GHz > DPO7000 Series

Application Notes and Technical Documents > Products > Oscilloscopes > Oscilloscopes up to 500MHz > DPO7000 Series

Application Notes and Technical Documents > Products > Oscilloscopes > Oscilloscopes 5GHz and above > DPO70000 Series

Application Notes and Technical Documents > Products > Oscilloscopes > Oscilloscopes 5GHz and above > DSA70000 Series

Application Notes and Technical Documents > Products > Oscilloscopes > Oscilloscopes 5GHz and above > DSA8200

Related Jitter, Noise & Link Analysis Information

Tektronix documents require the latest version of Adobe Acrobat Reader.